Welcome to Chuck's Home Page
"Dawn at the Ritz"
by Jerry Garcia
Skiing - The Cliff Club at Snowbird
Maui - The Maui Banyan
Austin Hill Country - Long Canyon
Scaling to the End of Silicon with EDGE Architectures (IEEE Computer)
Parting Thoughts - "Getting It Right" (IEEE Micro)
Parting Thoughts - "Design Convergence" (IEEE Micro)
Parting Thoughts - "Knowing When You Have a Problem" (IEEE Micro)
Scalable Hardware Memory Disambiguation for High ILP Processors (MICRO 2003)
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture (ISCA 2003)
A Wire-delay Scalable Microprocessor Architecture (ISSCC 2003)
"Moore, Moore and More" (by Peter Glaskowski, Microprocessor Report 2003)
Functional Verification - A Best-of-Breed Assessment (White paper, 2002)
"Lots and Lots of Threads" (Technical presentation, 2000)
"POWER4 System MicroArchitecture" (2000 Microprocessor Forum)
Server Oriented Microprocessor Design (Invited seminar talk at UT-Austin, 1999)
Design Considerations of the PowerPC 601 Microprocessor (IBM J of R and D, 1994)
The PowerPC 601 Microprocessor (IEEE Micro)
The PowerPC 601 Microprocessor (Compcon 1993)
The PowerPC Alliance (Communications of the ACM 1992)
IBM Single Chip RISC Processor (ICCD 1992)
IBM Second Generation RISC Machine Organization (ICCD 1989)
4,916,658 Dynamic buffer control
5,611,058 System and method for transferring information between multiple buses
5,603,057 System for initiating data transfer between input/output devices having separate address spaces in accordance with Initializing information in two address packages
5,500,950 Data processor with speculative data transfer and address-free retry
5,442,766 Method and system for distributed instruction address translation in a multiscalar data processing system
5,437,017 Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
5,127,091 System for reducing delay in instruction execution by executing branch instructions in separate processor
6,766,442 Processor and method that predict condition register dependent conditional branch instructions utilizing a potentially stale condition register value
6,748,519 Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register
6,728,866 Partitioned issue queue and allocation strategy
6,725,354 Shared execution unit in a dual core processor
6,678,820 Processor and method for separately predicting conditional branches dependent on lock acquisition
6,662,294 Converting short branches to predicated instructions
6,658,558 Branch prediction circuit selector with instruction context related condition type determining
6,658,555 Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline
6,654,869 Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling
6,625,746 Microprocessor instruction buffer redundancy scheme
6,609,190 Microprocessor with primary and secondary issue queue
5,848,283 Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization
5,793,986 Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system
5,724,565 Method and system for processing first and second sets of instructions by first and second types of processing systems
5,706,464 Method and system for achieving atomic memory references in a multilevel cache data processing system
5,692,218 System for transferring data between input/output devices having separate address spaces in accordance with initializing information in address packages
6,871,273 Processor and method of executing a load instruction dynamically bifurcate a load instruction into separately executable prefetch and register operations
6,868,491 Processor and method of executing load instructions out-of-order having reduced hazard penalty
6,829,702 Branch target cache and method for efficiently obtaining target path instructions for tight program loops
6,725,358 Processor and method having a load reorder queue that supports reservations
6,715,062 Processor and method for performing a hardware test during instruction execution in a normal mode
6,704,860 Data processing system and method for fetching instruction blocks in response to a detected block sequence
6,938,148 Managing load and store operations using a storage management unit with data flow architecture
My resume (2004)
chuck.moore at zmoore.net (e-mail me)